MC9S12KG128 Datasheet, PDF (163/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.5 Port H Registers
Port H is associated with two serial peripheral interfaces (SPI1, SPI2). Each pin is assigned to these
modules according to the following priority: SPI2/SP1 > general-purpose I/O.
When SPI2 is enabled, the respective pin configuration for PH[7:4] is determined by several status bits in
the SPI2 module. When SPI1 is enabled, the respective pin configuration for PH[3:0] is determined by
several status bits in the SPI1 module. Refer to the SPI block description chapter for information on
enabling and disabling the SPI. The SPI1 and SPI2 pins can be re-routed. Refer to Section 4.3.3.8,
“Module Routing Register (MODRR)”.
During reset, port H pins are configured as high-impedance inputs.
4.3.5.1 Port H I/O Register (PTH)
Module Base + 0x0020
7
R
PTH7
W
6
PTH6
5
PTH5
4
PTH4
3
PTH3
2
PTH2
SPI SS2
SCK2
MOSI2
MISO2
SS1
SCK1
Reset
0
0
0
0
0
0
Figure 4-31. Port H I/O Register (PTH)
Read: Anytime. Write: Anytime.
1
PTH1
MOSI1
0
0
PTH0
MISO1
0
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
The SPI function takes precedence over the general purpose I/O if enabled..
4.3.5.2 Port H Input Register (PTIH)
Module Base + 0x0021
7
R PTIH7
6
PTIH6
5
PTIH5
4
PTIH4
3
PTIH3
2
PTIH2
W
Reset
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-32. Port H Input Register (PTIH)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIH1
u
0
PTIH0
u
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
163