MC9S12KG128 Datasheet, PDF (512/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
REGS
ADDR
PK[7:0]/ECS/XCS/X[19:14]
Addr[19:0]
Data[15:0]
(Control)
CPU pipe info
IRQ interrupt
XIRQ interrupt
BDM tag info
EXT ^ADDR
BUS
I/F
DATA
CTL
ADDR
DATA
ECLK CTL
PIPE CTL
IRQ CTL
TAG CTL
mode
BKGD
PA[7:0]/A[15:8]/
D[15:8]/D[7:0]
PB[7:0]/A[7:0]/
D[7:0]
PE[7:2]/NOACC/
IPIPE1/MODB/CLKTO
IPIPE0/MODA/
ECLK/
LSTRB/TAGLO
R/W
PE1/IRQ
PE0/XIRQ
BKGD/MODC/TAGHI
Control signal(s)
Data signal (unidirectional)
Data signal (bidirectional)
Data bus (unidirectional)
Data bus (bidirectional)
Figure 18-1. MEBI Block Diagram
MC9S12KG128 Data Sheet, Rev. 1.15
512
Freescale Semiconductor