MC9S12KG128 Datasheet, PDF (115/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 128 Kbyte ECC Flash Module (FTS128K1ECCV1)
If a double bit fault is detected during array reads as part of the reset sequence, the ACCERR flag will set
in the FSTAT register.
2.7.2 Reset While Flash Command Active
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector / block being erased is not guaranteed.
2.8 Interrupts
The Flash module can generate an interrupt when all Flash command operations have completed, when the
Flash address, data, and command buffers are empty, or when a Flash array read or operation has detected
a double bit fault.
Table 2-20. Flash Interrupt Sources
Interrupt Source
Interrupt Flag
Local Enable
Global (CCR)
Mask
Flash Address, Data and Command
Buffers empty
All Flash commands completed
Flash array read or verify operation
detected a double bit fault
CBEIF
(FSTAT register)
CCIF
(FSTAT register)
DFDIF
(FSTAT register)
CBEIE
(FCNFG register)
I-Bit
CCIE
(FCNFG register)
I-Bit
DFDIE
(FCNFG register)
I-Bit
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
2.8.1 Description of Flash Interrupt Operation
The logic used for generating interrupts is shown in Figure 2-30.
The Flash module uses the CBEIF and CCIF flags in combination with the CBIE and CCIE enable bits to
generate the Flash command interrupt request. The Flash module uses the DFDIF flag in combination with
the DFDIE enable bit to generate the Flash double fault detect interrupt request.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
115