MC9S12KG128 Datasheet, PDF (149/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

4.3.2.2 Port S Input Register (PTIS)
Chapter 4 Port Integration Module (PIM9KG128V1)
Module Base + 0x0009
7
R PTIS7
6
PTIS6
5
PTIS5
4
PTIS4
3
PTIS3
2
PTIS2
W
Reset
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-9. Port S Input Register (PTIS)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIS1
u
0
PTIS0
u
4.3.2.3 Port S Data Direction Register (DDRS)
Module Base + 0x000A
R
W
Reset
7
DDRS7
0
6
DDRS6
0
5
DDRS5
0
4
DDRS4
0
3
DDRS3
0
2
DDRS2
0
Figure 4-10. Port S Data Direction Register (DDRS)
Read: Anytime. Write: Anytime.
1
DDRS1
0
0
DDRS0
0
This register configures each port S pin as either input or output.
When the SPI0 is enabled, the PS[7:4] pins become the SPI bidirectional pins. The associated Data
Direction Register bits have no effect.
When the SCI0(1) transmitter is enabled, the PS[1](PS[3]) pin becomes the TXD0(1) output pin and the
associated Data Direction Register bit has no effect. When the SCI0(1) receiver is enabled, the
PS[0](PS[2]) pin becomes the RXD0(1) input pin and the associated Data Direction Register bit has no
effect.
If the SPI0, SCI0 and SCI1 functions are disabled, the corresponding Data Direction Register bit reverts
to control the I/O direction of the associated pin.
Table 4-7. DDRS Field Descriptions
Field
7–0
Data Direction Port S
DDRS[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
149