MC9S12KG128 Datasheet, PDF (68/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 MC9S12KG128 Device Overview (MC9S12KG128V1)
map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin is latched
into the ROMON bit in the MISC register on the rising edge of the reset signal.
For further explanation on the modes refer to the HCS12 MEBI block description chapter.
BKGD =
MODC
0
PE6 =
MODB
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
PE5 =
MODA
0
1
0
1
0
1
0
1
Table 1-9. Mode Selection
PK7 =
ROMCTL
X
0
1
X
0
1
X
0
1
X
0
1
ROMON
Bit
1
1
0
0
1
0
1
0
1
1
0
1
Mode Description
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
Emulation Expanded Narrow, BDM allowed
Special Test (Expanded Wide), BDM allowed
Emulation Expanded Wide, BDM allowed
Normal Single Chip, BDM allowed
Normal Expanded Narrow, BDM allowed
Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
Normal Expanded Wide, BDM allowed
Table 1-10. Clock Selection Based on PE7
PE7 = XCLKS
Description
1
Loop Controlled Pierce Oscillator selected
0
Full Swing Pierce Oscillator or external clock selected
Table 1-11. Voltage Regulator VREGEN
VREGEN
1
0
Description
Internal Voltage Regulator enabled
Internal Voltage Regulator disabled, VDD1,2 and
VDDPLL must be supplied externally with 2.5V
MC9S12KG128 Data Sheet, Rev. 1.15
68
Freescale Semiconductor