SAM7S256_14 Datasheet, PDF (98/775 Pages) ATMEL Corporation – ARM-based Flash MCU

It is made up of:
• A bus arbiter
• An address decoder
• An abort status
• A misalignment detector
• An Embedded Flash Controller
The MC handles only little-endian mode accesses. The masters work in little-endian mode only.
18.3.1 Bus Arbiter
The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the
two masters. The Peripheral DMA Controller has the highest priority; the ARM processor has the lowest one.
18.3.2 Address Decoder
The Memory Controller features an Address Decoder that first decodes the four highest bits of the 32-bit address
bus and defines three separate areas:
• One 256-Mbyte address space for the internal memories
• One 256-Mbyte address space reserved for the embedded peripherals
• An undefined address space of 3584M bytes representing fourteen 256-Mbyte areas that return an Abort if
accessed
Figure 18-2 shows the assignment of the 256-Mbyte memory areas.
Figure 18-2. Memory Areas
256M Bytes
0x0000 0000
0x0FFF FFFF
0x1000 0000
Internal Memories
14 x 256MBytes
3,584 Mbytes
Undefined
(Abort)
256M Bytes
0xEFFF FFFF
0xF000 0000
0xFFFF FFFF
Peripherals
18.3.2.1 Internal Memory Mapping
Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more
address bits to allocate 1-Mbyte address spaces for the embedded memories.
The allocated memories are accessed all along the 1-Mbyte address space and so are repeated n times within this
address space, n equaling 1M bytes divided by the size of the memory.
When the address of the access is undefined within the internal memory area, the Address Decoder returns an
Abort to the master.
SAM7S Series [DATASHEET] 98
6175M–ATARM–26-Oct-12