SAM7S256_14 Datasheet, PDF (627/775 Pages) ATMEL Corporation – ARM-based Flash MCU

40.7.5 Power Management Controller (PMC)
40.7.5.1 PMC: Slow Clock Selected in PMC and a Transition Occurs on PA1
Under certain rare circumstances, when CSS = 00 in PMC_MCKR, and PA1 is set as an input and a transition
occurs on PA1, device malfunction might occur.
Problem Fix/Workaround
Do not transition PA1 as an input when CSS = 00 in PMC_MCKR.
40.7.5.2 PMC: Programming CSS in PMC_MCKR Register
Under certain rare circumstances, reprogramming the CSS value in the PMC_MCKR register (i.e switching the
main clock source) might generate malfunction of the device if the following two actions occur simultaneously.
1. Switching from:
– PLL Clock to Slow Clock or
– PLL Clock to Main Clock or
– Main Clock to PLL Clock or
– Main Clock to Slow Clock
And
2. Program code is being executed out of flash, or a transition is occurring on PA1, either as an input or
output.
Note: This issue does not occur when transitioning from slow clock to main clock or from slow clock to PLL clock.
Problem Fix/Workaround
When changing CSS in the PMC_MCKR to switch from
– PLL Clock to Slow Clock or
– PLL Clock to Main Clock or
– Main Clock to PLL Clock or
– Main Clock to Slow Clock
Ensure that the processor is executing out of SRAM and ensure no transition occurs on PA1, either as an input or
output, starting from writing to the PMC_MCKR register until MCKRDY = 1.
40.7.6 Pulse Width Modulation Controller (PWM)
40.7.6.1 PWM: Update when PWM_CCNTx = 0 or 1
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is
directly modified when writing the Channel Update Register.
Problem Fix/Workaround
Check the Channel Counter Register before writing the update register.
40.7.6.2 PWM: Update when PWM_CPRDx = 0
When Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround
Do not write 0 in the period register.
40.7.6.3 PWM: Counter Start Value
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1.
Problem Fix/Workaround
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
627