SAM7S256_14 Datasheet, PDF (352/775 Pages) ATMEL Corporation – ARM-based Flash MCU

30.10.6 TWI Status Register
Name:
TWI_SR
Access:
Read-only
Reset Value: 0x0000F009
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
EOSACC
SCLWS
ARBLST
NACK
7
6
5
4
3
2
1
0
–
OVRE
GACC
SVACC
SVREAD
TXRDY
RXRDY
TXCOMP
• TXCOMP: Transmission Completed (automatically set / reset)
TXCOMP used in Master mode:
0 = During the length of the current frame.
1 = When both holding and shifter registers are empty and STOP condition has been sent.
TXCOMP behavior in Master mode can be seen in Figure 30-8 on page 324 and in Figure 30-10 on page 325.
TXCOMP used in Slave mode:
0 = As soon as a Start is detected.
1 = After a Stop or a Repeated Start + an address different from SADR is detected.
TXCOMP behavior in Slave mode can be seen in Figure 30-27 on page 341, Figure 30-28 on page 342, Figure 30-29 on
page 343 and Figure 30-30 on page 343.
• RXRDY: Receive Holding Register Ready (automatically set / reset)
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
RXRDY behavior in Master mode can be seen in Figure 30-10 on page 325.
RXRDY behavior in Slave mode can be seen in Figure 30-25 on page 339, Figure 30-28 on page 342, Figure 30-29 on
page 343 and Figure 30-30 on page 343.
• TXRDY: Transmit Holding Register Ready (automatically set / reset)
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at
the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
TXRDY behavior in Master mode can be seen in Figure 30-8 on page 324.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
352