SAM7S256_14 Datasheet, PDF (509/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 35-6. Data IN Transfer for Non Ping-pong Endpoint
Prevous Data IN TX
Microcontroller Load Data in FIFO
Data is Sent on USB Bus
USB Bus Packets
Data IN
PID
Data IN 1
ACK
PID
Data IN
PID
NAK
PID
Data IN
PID
Data IN 2
ACK
PID
TXPKTRDY Flag
(UDP_CSRx)
Set by the firmware
Cleared by Hw
Set by the firmware
Cleared by Hw
TXCOMP Flag
(UDP_CSRx)
Interrupt Pending
Cleared by Firmware
Payload in FIFO
FIFO (DPR)
Content
Data IN 1
DPR access by the firmware
Load In Progress
DPR access by the hardware
Data IN 2
Interrupt
Pending
Cleared by
Firmware
35.5.2.4 Using Endpoints With Ping-pong Attribute
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows han-
dling the maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a
constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the
current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the
microcontroller, the other one is locked by the USB device.
Figure 35-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints
Microcontroller
USB Device
USB Bus
1st Data Payload
Write
Bank 0
Endpoint 1
Read
Read and Write at the Same Time
2nd Data Payload
3rd Data Payload
Bank 1
Endpoint 1
Bank 0
Endpoint 1
Bank 0
Endpoint 1
Bank 1
Endpoint 1
Data IN Packet
1st Data Payload
Data IN Packet
2nd Data Payload
Bank 0
Endpoint 1
Data IN Packet
3rd Data Payload
When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions:
1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the
endpoint’s UDP_ CSRx register.
2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte
values in the endpoint’s UDP_ FDRx register.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
509