SAM7S256_14 Datasheet, PDF (356/775 Pages) ATMEL Corporation – ARM-based Flash MCU

30.10.8 TWI Interrupt Disable Register
Name:
TWI_IDR
Access:
Write-only
Reset Value: 0x00000000
31
30
29
28
27
–
–
–
–
–
23
22
21
20
19
–
–
–
–
–
15
14
13
12
11
EOSACC
7
6
5
4
3
–
OVRE
GACC
SVACC
–
• TXCOMP: Transmission Completed Interrupt Disable
• RXRDY: Receive Holding Register Ready Interrupt Disable
• TXRDY: Transmit Holding Register Ready Interrupt Disable
• SVACC: Slave Access Interrupt Disable
• GACC: General Call Access Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• NACK: Not Acknowledge Interrupt Disable
• ARBLST: Arbitration Lost Interrupt Disable
• SCL_WS: Clock Wait State Interrupt Disable
• EOSACC: End Of Slave Access Interrupt Disable
0 = No effect.
1 = Disables the corresponding interrupt.
26
–
18
–
10
SCL_WS
2
TXRDY
25
–
17
–
9
ARBLST
1
RXRDY
24
–
16
–
8
NACK
0
TXCOMP
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
356