SAM7S256_14 Datasheet, PDF (335/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 30-20. Programmer Sends Data While the Bus is Busy
TWCK
TWD
TWI DATA transfer
STOP sent by the master
START sent by the TWI
DATA sent by a master
Bus is busy
Transfer is kept
Bus is free
DATA sent by the TWI
A transfer is programmed
(DADR + W + START + Write THR)
Figure 30-21. Arbitration Cases
TWCK
TWD
Bus is considered as free
Transfer is initiated
TWCK
Data from a Master
Data from TWI
TWD
S 1 0 0 11
P
S 101
Arbitration is lost
TWI stops sending data
S 1 0 0 _{1 1} Data from the master P
S
1
Arbitration is lost
01
The master stops sending data
S 1 0 01 ₁
S 1 0 0 1 1 Data from the TWI
ARBLST
Bus is busy
Bus is free
TWI DATA transfer
Transfer is kept
A transfer is programmed
(DADR + W + START + Write THR)
Transfer is stopped
Transfer is programmed again
(DADR + W + START + Write THR)
Bus is considered as free
Transfer is initiated
The flowchart shown in Figure 30-22 on page 336 gives an example of read and write operations in Multi-master
mode.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
335