SAM7S256_14 Datasheet, PDF (365/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 31-5. Baud Rate Generator
USCLKS
MCK
0
MCK/DIV
1
Reserved
SCK
2
3
CD
CD
16-bit Counter
>1
1
0
0
0
1
SYNC
USCLKS = 3
SCK
FIDI
OVER
Sampling
Divider
SYNC
0
Baud Rate
Clock
1
Sampling
Clock
31.6.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is
field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver
as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sam-
pling is performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
Baudrate = --^S-----^e---^l--^e----^c---^t--^e----^d----^C----^l--^o----^c---^k---
(8(2 – Over)CD)
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that
OVER is programmed at 1.
31.6.1.2 Baud Rate Calculation Example
Table 31-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies.
This table also shows the actual resulting baud rate and the error.
Table 31-2. Baud Rate Example (OVER = 0)
Expected Baud
Source Clock
Rate
Calculation Result
CD
MHz
Bit/s
3 686 400
38 400
6.00
6
4 915 200
38 400
8.00
8
5 000 000
38 400
8.14
8
7 372 800
38 400
12.00
12
8 000 000
38 400
13.02
13
12 000 000
38 400
19.53
20
12 288 000
38 400
20.00
20
14 318 180
38 400
23.30
23
Actual Baud Rate
Bit/s
38 400.00
38 400.00
39 062.50
38 400.00
38 461.54
37 500.00
38 400.00
38 908.10
Error
0.00%
0.00%
1.70%
0.00%
0.16%
2.40%
0.00%
1.31%
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
365