SAM7S256_14 Datasheet, PDF (195/775 Pages) ATMEL Corporation – ARM-based Flash MCU

wait (MCKRDY=1)
The Master Clock is main clock divided by 16.
The Processor Clock is the Master Clock.
5. Selection of Programmable clocks
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers.
Depending on the system used, 3 Programmable clocks can be enabled or disabled. The PMC_SCSR pro-
vides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are
disabled.
PMC_PCKx registers are used to configure Programmable clocks.
The CSS field is used to select the Programmable clock divider source. Four clock options are available: main
clock, slow clock, PLLCK. By default, the clock source selected is slow clock.
The PRES field is used to control the Programmable clock prescaler. It is possible to choose between different
values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By
default, the PRES parameter is set to 1 which means that master clock is equal to slow clock.
Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be
enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be
done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to
PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a
single write operation.
If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled
first. The parameters can then be modified. Once this has been done, the user must re-enable the Programma-
ble clock and wait for the PCKRDYx bit to be set.
Code Example:
write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32.
6. Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via
registers PMC_PCER and PMC_PCDR.
Depending on the system used, SAM7S512/256/128/64/321, 12 and for SAM7S32/16, 10 peripheral clocks
can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled.
Note: Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
195