SAM7S256_14 Datasheet, PDF (577/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 37-7. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
MISO
MOSI
SPI₉
SPI₁₀
SPI₁₁
Table 37-22. SPI Timings
Symbol
Parameter
SPI₀
MISO Setup time before SPCK rises (master)
SPI₁
MISO Hold time after SPCK rises (master)
SPI₂
SPCK rising to MOSI Delay (master)
SPI₃
MISO Setup time before SPCK falls (master)
SPI₄
MISO Hold time after SPCK falls (master)
SPI₅
SPCK falling to MOSI Delay (master)
SPI₆
SPCK falling to MISO Delay (slave)
SPI₇
MOSI Setup time before SPCK rises (slave)
SPI₈
MOSI Hold time after SPCK rises (slave)
SPI₉
SPCK rising to MISO Delay (slave)
SPI₁₀
MOSI Setup time before SPCK falls (slave)
SPI₁₁
MOSI Hold time after SPCK falls (slave)
Conditions
3.3V domain⁽¹⁾
1.8V domain⁽²⁾
3.3V domain⁽¹⁾
1.8V domain⁽²⁾
3.3V domain⁽¹⁾
1.8V domain⁽²⁾
3.3V domain⁽¹⁾
1.8V domain⁽²⁾
3.3V domain ⁽¹⁾
1.8V domain ⁽²⁾
3.3V domain ⁽¹⁾
1.8V domain ⁽²⁾
3.3V domain ⁽¹⁾
1.8V domain ⁽²⁾
3.3V domain ⁽¹⁾
1.8V domain ⁽²⁾
3.3V domain ⁽¹⁾
1.8V domain ⁽²⁾
3.3V domain ⁽¹⁾
1.8V domain ⁽²⁾
3.3V domain ⁽¹⁾
1.8V domain ⁽²⁾
3.3V domain ⁽¹⁾
1.8V domain ⁽²⁾
Min
28.5 + (t_CPMCK)/2⁽³⁾
38 + (t_CPMCK)/2⁽³⁾
0
0
26.5 + (t_CPMCK)/2⁽³⁾
44 + (t_CPMCK)/2⁽³⁾
0
0
2
3
3
2
3
3
3
2
Max
2
7
2
2.5
28
44
28
43
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. 3.3V domain: V_VDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF.
2. 1.8V domain: V_VDDIO from 1.65V to 1.95V, maximum external capacitor = 20 pF.
3. t_CPMCK: Master Clock period in ns.
Note that in SPI master mode the ATSAM7S512/256/128/64/321/32 does not sample the data (MISO) on the
opposite edge where data clocks out (MOSI) but the same edge is used as shown in Figure 37-4 and Figure 37-5.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
577