SAM7S256_14 Datasheet, PDF (301/775 Pages) ATMEL Corporation – ARM-based Flash MCU

29.6.5
Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
29.6.5.1
7-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 29-10, Figure
29-11 and Figure 29-12.
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
In the figures below the following abbreviations are used:
•S
•P
•W
•R
•A
•N
• DADR
• IADR
Start
Stop
Write
Read
Acknowledge
Not Acknowledge
Device Address
Internal Address
Figure 29-10. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address
TWD
S
DADR
W
A IADR(23:16) A IADR(15:8) A
IADR(7:0)
A
DATA
Two bytes internal address
TWD
S
DADR
W
A IADR(15:8) A
IADR(7:0)
A
DATA
A
P
One byte internal address
TWD
S
DADR
W
A
IADR(7:0)
A
DATA
A
P
A
P
Figure 29-11. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address
TWD S
DADR
W
A IADR(23:16) A IADR(15:8) A IADR(7:0) A
S
DADR
R
A
Two bytes internal address
TWD S
DADR
W
A IADR(15:8) A
IADR(7:0) A
S
DADR
DATA
N
P
R
A
DATA
NP
One byte internal address
TWD S
DADR
W
A IADR(7:0) A
S DADR R
A
DATA
N
P
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
301