SAM7S256_14 Datasheet, PDF (59/775 Pages) ATMEL Corporation – ARM-based Flash MCU

13.3.2.2 NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out”
signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion
duration, named EXTERNAL_RESET_LENGTH, lasts 2^(ERSTL+1) Slow Clock cycles. This gives the approximate
duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the
NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is
driven low for a time compliant with potential external devices connected on the system reset.
13.3.3 Brownout Manager
Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below
a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout
reset by asserting the bod_reset signal.
The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the cor-
responding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed.
Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when
RSTC_SR is read.
The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR.
At factory, the brownout reset is disabled.
Figure 13-3. Brownout Manager
bod_rst_en
bod_reset
brown_out
RSTC_SR
BODSTS
RSTC_MR
BODIEN
Other
interrupt
sources
rstc_irq
SAM7S Series [DATASHEET] 59
6175M–ATARM–26-Oct-12