SAM7S256_14 Datasheet, PDF (342/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Clock Synchronization in Write Mode
The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was
not detected, it is tied low until TWI_RHR is read.
Figure 30-28 on page 342 describes the clock synchronization in Read mode.
Figure 30-28. Clock Synchronization in Write Mode
TWCK
TWD
CLOCK is tied low by the TWI as long as RHR is full
S SADR W A DATA0 A DATA1
A DATA2 NA S ADR
TWI_RHR
DATA0 is not read in the RHR
DATA1
DATA2
SCLWS
RXRDY
SVACC
SVREAD
TXCOMP
As soon as a START is detected
SCL is stretched on the last bit of DATA1
Rd DATA0
Rd DATA1 _{Rd DATA2}
Notes:
1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from
SADR.
2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mecha-
nism is finished.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
342