SAM7S256_14 Datasheet, PDF (113/775 Pages) ATMEL Corporation – ARM-based Flash MCU

• When the bit is set, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an interrupt has
been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: A bad keyword and/or an invalid command have been written in the MC_FCR register
• If the general-purpose bit number is greater than the total number of general-purpose bits, then the command
has no effect.
It is possible to deactivate a general-purpose NVM bit set previously. The clear sequence is:
• Start the Clear General-purpose Bit command (CGPB) by writing the Flash Command Register with CGPB and
the number of the general-purpose bit to be cleared in the PAGEN field.
• When the clear completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an
interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is
activated.
Two errors can be detected in the MC_FSR register after a programming sequence:
• Programming Error: a bad keyword and/or an invalid command have been written in the MC_FCR register
• If the number of the general-purpose bit set in the PAGEN field is greater than the total number of general-
purpose bits, then the command has no effect.
The Clear General-purpose Bit command programs the general-purpose NVM bit to 0; the corresponding bit
GPNVM0 to GPNVMx in MC_FSR reads 0. The Set General-purpose Bit command programs the general-purpose
NVM bit to 1; the corresponding bit GPNVMx in MC_FSR reads 1.
Note: Access to the Flash in read mode is permitted when a Set, Clear or Get General-purpose NVM Bit command is
performed.
19.2.4.5 Security Bit
The goal of the security bit is to prevent external access to the internal bus system. (Does not apply to EFC1 on
theSAM7S512.) JTAG, Fast Flash Programming and Flash Serial Test Interface features are disabled. Once set,
this bit can be reset only by an external hardware ERASE request to the chip. Refer to the product definition sec-
tion for the pin name that controls the ERASE. In this case, the full memory plane is erased and all lock and
general-purpose NVM bits are cleared. The security bit in the MC_FSR is cleared only after these operations. The
activation sequence is:
• Start the Set Security Bit command (SSB) by writing the Flash Command Register.
• When the locking completes, the bit FRDY in the Flash Programming Status Register (MC_FSR) rises. If an
interrupt has been enabled by setting the bit FRDY in MC_FMR, the interrupt line of the Memory Controller is
activated.
When the security bit is active, the SECURITY bit in the MC_FSR is set.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
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