SAM7S256_14 Datasheet, PDF (25/775 Pages) ATMEL Corporation – ARM-based Flash MCU

8.8.6
Calibration Bits
Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured
and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.
8.9 Fast Flash Programming Interface
The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through
a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.
The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.
The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the
PA0 and PA1 pins are all tied high and PA2 is tied low.
8.10
SAM-BA Boot Assistant
The SAM-BA^® Boot Recovery restores the SAM-BA Boot in the first two sectors of the on-chip Flash memory. The
SAM-BA Boot recovery is performed when the TST pin and the PA0, PA1 and PA2 pins are all tied high for 10 sec-
onds. Then, a power cycle of the board is mandatory.
The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash
memory.
The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port. (The
SAM7S32/16 have no USB Device Port.)
z Communication through the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-
detection.
z Communication through the USB Device Port is limited to an 18.432 MHz crystal. (
The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).
9. System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset.
The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF
F000 and 0xFFFF FFFF.
Figure 9-1 on page 26 and Figure 9-2 on page 27 show the product specific System Controller Block Diagrams.
Figure 8-1 on page 20 shows the mapping of the of the User Interface of the System Controller peripherals. Note that the
memory controller configuration user interface is also mapped within this address space.
SAM7S Series [DATASHEET] 25
6175M–ATARM–26-Oct-12