SAM7S256_14 Datasheet, PDF (153/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data
transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are
loaded into the Counter/Pointer registers in order to re-enable the triggers.
For each channel, two status bits indicate the end of the current buffer (ENDRX, ENDTX) and the end of both cur-
rent and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the peripheral status register and can
trigger an interrupt request to the AIC.
The peripheral end flag is automatically cleared when one of the counter-registers (Counter or Next Counter Reg-
ister) is written.
Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero.
22.3.4 Data Transfers
The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals.
When the peripheral receives an external character, it sends a Receive Ready signal to the PDC which then
requests access to the system bus. When access is granted, the PDC starts a read of the peripheral Receive Hold-
ing Register (RHR) and then triggers a write in the memory.
After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decre-
mented. When the memory block size is reached, a signal is sent to the peripheral and the transfer stops.
The same procedure is followed, in reverse, for transmit transfers.
22.3.5 Priority of PDC Transfer Requests
The Peripheral DMA Controller handles transfer requests from the channel according to priorities fixed for each
product.These priorities are defined in the product datasheet.
If simultaneous requests of the same type (receiver or transmitter) occur on identical peripherals, the priority is
determined by the numbering of the peripherals.
If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers
are handled first and then followed by transmitter requests.
22.4 Peripheral DMA Controller (PDC) User Interface
Table 22-1. Register Mapping
Offset
0x100
Register
Receive Pointer Register
Register Name
PERIPH⁽¹⁾_RPR
Access
Read-write
Reset
0x0
0x104
Receive Counter Register
PERIPH_RCR
Read-write
0x0
0x108
Transmit Pointer Register
PERIPH_TPR
Read-write
0x0
0x10C
Transmit Counter Register
PERIPH_TCR
Read-write
0x0
0x110
Receive Next Pointer Register
PERIPH_RNPR
Read-write
0x0
0x114
Receive Next Counter Register
PERIPH_RNCR
Read-write
0x0
0x118
Transmit Next Pointer Register
PERIPH_TNPR
Read-write
0x0
0x11C
Transmit Next Counter Register
PERIPH_TNCR
Read-write
0x0
0x120
PDC Transfer Control Register
PERIPH_PTCR
Write-only
-
0x124
PDC Transfer Status Register
PERIPH_PTSR
Read-only
0x0
Note: 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user
according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc).
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
153