SAM7S256_14 Datasheet, PDF (529/775 Pages) ATMEL Corporation – ARM-based Flash MCU

35.6.10 UDP Endpoint Control and Status Register
Register Name:
UDP_ CSRx [x = 0..Y]
Access Type:
Read-write
31
30
29
28
27
–
–
–
–
–
26
25
24
RXBYTECNT
23
22
21
20
19
18
17
16
RXBYTECNT
15
14
13
12
11
10
9
8
EPEDS
–
–
–
DTGLE
EPTYPE
7
6
5
4
3
2
1
0
DIR
RX_DATA_
BK1
FORCE
STALL
TXPKTRDY
STALLSENT
ISOERROR
RXSETUP
RX_DATA_
BK0
TXCOMP
WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write
operation before executing another write by polling the bits which must be set/cleared.
//! Clear flags of UDP UDP_CSR register and waits for synchronization
#define Udp_ep_clr_flag(pInterface, endpoint, flags) { \
pInterface->UDP_CSR[endpoint] &= ~(flags); \
while ( (pInterface->UDP_CSR[endpoint] & (flags)) == (flags) ); \
}
//! Set flags of UDP UDP_CSR register and waits for synchronization
#define Udp_ep_set_flag(pInterface, endpoint, flags) { \
pInterface->UDP_CSR[endpoint] |= (flags); \
while ( (pInterface->UDP_CSR[endpoint] & (flags)) != (flags) ); \
}
Note:
In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and 1peripheral clock cycle. How-
ever, RX_DATA_BLK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK clock cycles and 3 peripheral clock cycles
before accessing DPR.
• TXCOMP: Generates an IN Packet with Data Previously Written in the DPR
This flag generates an interrupt while it is set to one.
Write (Cleared by the firmware):
0 = Clear the flag, clear the interrupt.
1 = No effect.
Read (Set by the USB peripheral):
0 = Data IN transaction has not been acknowledged by the Host.
1 = Data IN transaction is achieved, acknowledged by the Host.
After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the
host has acknowledged the transaction.
• RX_DATA_BK0: Receive Data Bank 0
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
529