SAM7S256_14 Datasheet, PDF (97/775 Pages) ATMEL Corporation – ARM-based Flash MCU

18. Memory Controller (MC)
18.1
Overview
The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the
ARM7TDMI processor and the Peripheral DMA Controller. It features a simple bus arbiter, an address decoder, an
abort status, a misalignment detector and an Embedded Flash Controller.
18.2 Block Diagram
Figure 18-1. Memory Controller Block Diagram
Memory Controller
ARM7TDMI
Processor _Abort
ASB
Abort
Status
Embedded
Flash
Controller
Internal
Flash
Internal
RAM
Bus
Arbiter
Misalignment
Detector
Address
Decoder
Peripheral
DMA
Controller
User
Interface
Peripheral 0
Peripheral 1
Peripheral N
APB
Bridge
APB
From Master
to Slave
18.3 Functional Description
The Memory Controller handles the internal ASB bus and arbitrates the accesses of both masters.
SAM7S Series [DATASHEET] 97
6175M–ATARM–26-Oct-12