SAM7S256_14 Datasheet, PDF (52/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Table 12-2. SAM7S Series Debug Unit Chip ID (Continued)
AT91SAM7S128 Rev B
AT91SAM7S128 Rev C
AT91SAM7S128 Rev D
AT91SAM7S256 Rev A
AT91SAM7S256 Rev B
AT91SAM7S256 Rev C
AT91SAM7S256 Rev D
AT91SAM7S512 Rev A
AT91SAM7S512 Rev B
0x270A0741
0x270A0742
0x270A0743
0x270D0940
0x270B0941
0x270B0942
0x270B0943
0x270B0A40
0x270B0A4F
For further details on the Debug Unit, see the Debug Unit section.
12.5.4 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.
IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS func-
tions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies
the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.
It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAG-
SEL is changed.
A Boundary-scan Descriptor Language (BSDL) file is provided to set up testing.
12.5.4.1 JTAG Boundary-scan Register
The Boundary-scan Register (BSR) contains 96 bits that correspond to active pins and associated control signals.
Each SAM7Sxx input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that
can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit
selects the direction of the pad.
Table 12-3. SAM7Sxx JTAG Boundary Scan Register
Bit Number
96
95
94
93
92
91
90
89
88
Pin Name
PA17/PGMD5/AD0
PA18/PGMD6/AD1
PA21/PGMD9*
Pin Type
IN/OUT
IN/OUT
IN/OUT*
Associated BSR
Cells
INPUT
OUTPUT
CONTROL
INPUT
OUTPUT
CONTROL
INPUT⁽¹⁾
OUTPUT⁽¹⁾
CONTROL⁽¹⁾
SAM7S Series [DATASHEET] 52
6175M–ATARM–26-Oct-12