SAM7S256_14 Datasheet, PDF (690/775 Pages) ATMEL Corporation – ARM-based Flash MCU

40.17.2 Non Volatile Memory Bits (NVM Bits)
40.17.2.1 NVM Bits: Write/Erase Cycles Number
The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes Lock Bits (LOCKx),
General Purpose NVM bits (GPNVMx) and the Security Bit.
This maximum number of write/erase cycles is not applicable to 64 KB Flash memory, it remains at10K for the
Flash memory.
Problem Fix/Workaround
None.
40.17.3 Parallel Input/Output Controller (PIO)
40.17.3.1 PIO: Leakage on PA17 - PA20
When PA17, PA18, PA19 or PA20 (the I/O lines multiplexed with the analog inputs) are set as digital inputs with
pull-up disabled, the leakage can be 9 µA in worst case and 90 nA in typical case per I/O when the I/O is set exter-
nally at low level.
Problem Fix/Workaround
Set the I/O to VDDIO by internal or external pull-up.
40.17.3.2 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31
When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabi-
lizes at VPull-up.
Vpull-up
VPull-up Min
VDDIO - 0.65 V
VPull-up Max
VDDIO - 0.45 V
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V, and 25 µA
at 1.8V.
I Leakage
Parameter
I Leakage at 3,3V
I Leakage at 1.8V
Typ
2.5 µA
1 µA
Max
45 µA
25 µA
Problem Fix/Workaround
It is recommended to use an external pull-up if needed.
40.17.3.3 PIO: Drive Low NRST, PA0-PA16 and PA21-PA31
When NRST or PA0-PA16 and or PA21-PA31 are set as digital inputs with pull-up enabled, driving the I/O with an
output impedance higher than 500 ohms may not drive the I/O to a logical zero.
Problem Fix/Workaround
Output impedance must be lower than 500 ohms.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
690