SAM7S256_14 Datasheet, PDF (642/775 Pages) ATMEL Corporation – ARM-based Flash MCU

40.9 SAM7S256 Errata - Revision C Parts
Refer to Section 40.1 “Marking” on page 595.
Note: AT91SAM7S256 Revision C chip ID is 0x270B 0942.
40.9.1 Embedded Flash Controller (EFC)
40.9.1.1 EFC: Embedded Flash Access Time 1
The embedded Flash maximum access time is 20 MHz (instead of 30 MHz) at zero Wait State (FWS = 0).
The maximum operating frequency with one Wait State (FWS = 1) is 48.1 MHz (instead of 55 MHz). Above 48.1
MHz and up to 55 MHz, two Wait States (FWS = 2) are required.
Problem Fix/Workaround
Set the number of Wait States (FWS) according to the frequency requirements described in this errata.
40.9.2 Parallel Input/Output Controller (PIO)
40.9.2.1 PIO: Electrical Characteristics on NRST and PA0-PA16 and PA21-31
When NRST or PA0-PA16 or PA21-PA31 are set as digital inputs with pull-up enabled, the voltage of the I/O stabi-
lizes at VPull-up.
Vpull-up
VPull-up Min
VDDIO - 0.65 V
VPull-up Max
VDDIO - 0.45 V
This condition causes a leakage through VDDIO. This leakage is 45 µA per pad in worst case at 3.3 V, and 25 µA
at 1.8V.
I Leakage
Parameter
I Leakage at 3,3V
I Leakage at 1.8V
Typ
2.5 µA
1 µA
Max
45 µA
25 µA
Problem Fix/Workaround
It is recommended to use an external pull-up if needed.
40.9.2.2 PIO: Drive Low NRST, PA0-PA16 and PA21-PA31
When NRST or PA0-PA16 and or PA21-PA31 are set as digital inputs with pull-up enabled, driving the I/O with an
output impedance higher than 500 ohms may not drive the I/O to a logical zero.
Problem Fix/Workaround
Output impedance must be lower than 500 ohms.
40.9.3 Pulse Width Modulation Controller (PWM)
40.9.3.1 PWM: Update when PWM_CCNTx = 0 or 1
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is
directly modified when writing the Channel Update Register.
Problem Fix/Workaround
Check the Channel Counter Register before writing the update register.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
642