SAM7S256_14 Datasheet, PDF (614/775 Pages) ATMEL Corporation – ARM-based Flash MCU

The transmitter may use the timeguard feature or send two STOP conditions. Only one STOP condition is taken
into account by the receiver state machine. After this STOP condition, as there is no valid data, the receiver state
machine will go in idle mode and enable the RXBRK flag.
40.5.9.5 USART: DCD is active High instead of Low
The DCD signal is active at High level in the USART Modem Mode.
DCD should be active at Low level.
Problem Fix/Workaround
Add an inverter.
40.6 SAM7S256 Errata - Manufacturing Number 58818C
Refer to Section 40.1 “Marking” on page 595.
Important: Section 40.6.14.1 ”WDT: The Watchdog Timer May Lock the Device in a Reset State”
40.6.1 Chip ID
40.6.1.1 Wrong Chip ID Value
The Chip ID is 0x270D0940 instead of 0x270B0940.
Problem Fix/Workaround
None.
40.6.2 Analog-to-Digital Converter (ADC)
40.6.2.1 ADC: DRDY Bit Cleared
The DRDY Flag should be clear only after a read of ADC_LCDR (Last Converted Data Register). A read of any
ADC_CDRx register (Channel Data Register) automatically clears the DRDY flag.
Problem Fix/Workaround:
None
40.6.2.2 ADC: DRDY not Cleared on Disable
When reading LCDR at the same instant as an end of conversion, with DRDY already active, DRDY is kept active
regardless of the enable status of the current channel. This sets DRDY, whereas new data is not stored.
Problem Fix/Workaround
None
40.6.2.3 ADC: DRDY Possibly Skipped due to CDR Read
Reading CDR for channel “y” at the same instant as an end of conversion on channel “x” with EOC[x] already
active, leads to skipping to set the DRDY flag if channel “x” is enabled.
Problem Fix/Workaround
Use of DRDY functionality with access to CDR registers should be avoided.
40.6.2.4 ADC: Possible Skip on DRDY when Disabling a Channel
DRDY does not rise when disabling channel “y” at the same time as an end of “x” channel conversion, although
data is stored into CDRx and LCDR.
Problem Fix/Workaround
None.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
614