SAM7S256_14 Datasheet, PDF (713/775 Pages) ATMEL Corporation – ARM-based Flash MCU

40.20.6 Synchronous Serial Controller (SSC)
40.20.6.1 SSC: Periodic Transmission Limitations in Master Mode
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.
40.20.6.2 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as output and TF is programmed as input, it is impossible to emit data when the start of edge
(rising or falling) of synchro has a Start Delay equal to zero.
Problem Fix/Workaround
None.
40.20.6.3 SSC: Transmitter Limitations in Slave Mode
If TK is programmed as an input and TF is programmed as an output and requested to be set to low/high during
data emission, the Frame Synchro signal is generated one bit clock period after the data start and one data bit is
lost. This problem does not exist when generating a periodic synchro.
Problem Fix/Workaround
The data need to be delayed for one bit clock period with an external assembly.
In the following schematic, TD, TK and NRST are SAM7S signals, TXD is the delayed data to connect to the
device.
40.20.7 Two-wire Interface (TWI)
40.20.7.1 TWI: Clock Divider
The value of CLDIV x 2^CKDIV must be less than or equal to 8191, the value of CHDIV x 2^CKDIV must be less than or
equal to 8191⋅
Problem Fix/Workaround
None.
40.20.7.2 TWI: Software Reset
When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new trans-
fer in READ or WRITE mode.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
713