SAM7S256_14 Datasheet, PDF (758/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Version
6175H
Comments (Continued)
Change
Request
Ref.
UDP:
Table 35-2, “USB Communication Flow”, Supported Endpoint column updated
In the USB_CSR register, the control endpoints are not effected by the fit field, “EPEDS: Endpoint Enable
Disable” on page 533,
Updated: write1 =....in “RX_DATA_BK0: Receive Data Bank 0” bit field of USB_CSR register.
Updated: write1 =....in “TXPKTRDY: Transmit Packet Ready” bit field of USB_CSR register.
Section 35.6.10 ”UDP Endpoint Control and Status Register” update to code and added instructions regarding
USB clock and system clock cycle, and updated “note” appearing under the code. “wait 3 USB clock cycles and
3 system clock cycles before accessing DPR from RX_DATAx and TXPKTRDY bit
fields, ditto for RX_DATAx and TXPKTRDY bit field descriptions.”
Section 35.2 ”Block Diagram”, in the text below the block diagram, MCK specified as clock used by Master
Clock domain, UDPCK specified as 48 MHz clock used by 12 MHz domain, in peripheral clock requirements.
Section 35.6 ”USB Device Port (UDP) User Interface”, The register mapping table has been updated.
Section 35.6.6 ”UDP Interrupt Mask Register”, bit field 12 has been defined as BIT12 and cannot be masked.
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4063
4099
4462
4487
4508
4802
USART:
“USCLKS: Clock Selection” on page 391, bit field in US_MR register, DIV=8 in “Selected Clock” column
Section 31.5.1 ”I/O Lines” 2nd and 3rd paragraphs updated.
“TXEMPTY: TXEMPTY Interrupt Enable” on page 394, no characters when at 1, updated bit field in US_CSR
Section 31.6.2 ”Receiver and Transmitter Control”, In 4th paragraph, “replaced 2nd sentence: The software
resets clear the...”
Section 31.6.5 ”IrDA Mode”, updated with instruction to receive IrDA signals.
Section 31.2 ”Block Diagram”, signal directions from pads to PIO updated in the block diagrams.
Section 31.6.3.1 ”Transmitter Operations”, last (4th) paragraph updated.
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4912
4905
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Electrical/Mechanical Characteristics,
Table 37-10, “Main Oscillator Characteristics”, added schematic in footnote to C_L and C_LEXT symbols.
Table 37-12, “XIN Clock Electrical Characteristics”, updated
Figure 37-2 ”XIN Clock Timing” added below table 36-12
Section 37.2 ”DC Characteristics”and Section 38. ”Mechanical Characteristics”, removed reference to T_J.
ADC Characteristics: Table 37-21, “Transfer Characteristics” INL and DN updated, linked reference to Data
Converter Terminology added below table.
Table 38-5, “LQFP and QFN Package Characteristics” JESD97 Classification updated to be e3.
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3965
4656
4006
4969
Table 37-7, “Power Consumption for Different Modes”, updated and expanded ARM core clock information.
Section 37.6 ”Master Clock Characteristics”, moved from former location.
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Section 37.7 ”I/O Characteristics”, moved from former location.
Section 40. ”Errata”, added the following:
Section 40.4 ”SAM7S512 Errata - Revision A Parts” provides list of errata with links.
Section 40.8 ”SAM7S256 Errata - Revision B Parts”
Section 40.13 ”SAM7S128 Errata - Revision B Parts”
Section 40.12 ”AT91SAM7S64 Errata - Revision B Parts”
Section 40.22 ”SAM7S32 Errata - Revision A Parts”
Section 40.23 ”SAM7S32 Errata - Revision B Parts”
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4325
4772
AT91SAM7S16/161:
Section 40.24 ”SAM7S161 Errata - Revision A Parts”
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Section 40.25 ”SAM7S16 Errata - Revision A Parts”
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
758