SAM7S256_14 Datasheet, PDF (721/775 Pages) ATMEL Corporation – ARM-based Flash MCU

selected Chip select is. For example, if SPI_CSR0 is configured for a 10-bit transfer whereas SPI_CSR1 is config-
ured for an 8-bit transfer, when a transfer is performed in Fixed mode through the PDC, on Chip select 1, the
transfer will be considered as a HalfWord transfer.
Problem Fix/Workaround
If a PDC transfer has to be performed in 8 bits, on a Chip select y (y as different from 0), the BITS field of the
SPI_CSR0 must be configured in 8 bits, in the same way as the BITS field of the CSRy Register.
40.21.7.6 SPI: Baudrate Set to 1
When Baudrate is set at 1 (i.e. when serial clock frequency equals the system clock frequency) and when the BITS
field of the SPI_CSR register (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15),
an additional pulse will be generated on output SPCK.
Everything is OK if the BITS field equals 8,10,12,14 or 16 and Baudrate = 1.
Problem Fix/Workaround
None.
40.21.7.7 SPI: Disable In Slave Mode
The SPI disable is not possible in slave mode.
Problem Fix/Workaround
Read first the received data, then perform the software reset.
40.21.7.8 SPI: Disable Issue
The SPI Command “SPI Disable” is not possible during a transfer, it must be performed only after TX_EMPTY ris-
ing else there is everlasting dummy transfers occur.
Problem Fix/Workaround
None.
40.21.7.9 SPI: Software Reset and SPIEN Bit
The SPI Command “software reset” does not reset the SPIEN config bit. Therefore rewriting an SPI enable com-
mand does not set TX_READY, TX_EMPTY flags.
Problem Fix/Workaround
Send SPI disable command after a software reset.
40.21.7.10 SPI: CSAAT = 1 and Delay
If CSAAT = 1 for current access and there is no more TX request for a time greater than DLYBCT + DLYBCS, then
if an access is requested on another slave, the NPCS bus switches from one CS to the one requested without
DLYBCS. External Slaves may reach a contention on SPI_MISO line for a short period.
Problem Fix/Workaround
Assert the Last Transfer Command (NPCS de-activation) for the last character of each slave.
40.21.7.11 SPI: Bad Serial Clock Generation on 2nd Chip Select
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when serial clock
frequency equals the system clock frequency) and the other transfers set with SCBR are not equal to 1
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
721