SAM7S256_14 Datasheet, PDF (720/775 Pages) ATMEL Corporation – ARM-based Flash MCU

40.21.6.4 PWM: Constraints on Duty Cycle Value
Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode
may change the polarity of the signal.
Problem Fix/Workaround
Do not set PWM_CDTYx at 0 in center aligned mode.
Do not set PWM_CDTYx at 0 or 1 in left aligned mode.
40.21.6.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the
PWM_DIS Register just after enabling it (before completion of a Clock Period of the clock selected for the channel),
the PWM line is internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
Problem Fix/Workaround
Do not disable a channel before completion of one period of the selected clock.
40.21.7 Serial Peripheral Interface (SPI)
40.21.7.1 SPI: Pulse Generation on SPCK
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows:
– The Baudrate is odd and different from 1
– The Polarity is set to 1
– The Phase is set to 0
Problem Fix/Workaround
None.
40.21.7.2 SPI: Bad tx_ready behavior when CSAAT=1 and SCBR = 1
If the SPI is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on
the same slave with an IDLE state between them, the tx_ready signal does not rise after the second data has been
transferred in the shifter. This can imply for example, that the second data is sent twice.
Problem Fix/Workaround
Do not use the combination CSAAT=1 and SCBR =1.
40.21.7.3 SPI: LASTXFER (Last Transfer) behavior
In FIXED Mode, with CSAAT bit set, and in “PDC mode” the Chip Select can rise depending on the data written in
the SPI_TDR when the TX_EMPTY flag is set. If for example, the PDC writes a “1” in the bit 24 (LASTXFER bit) of
the SPI_TDR, the chip select will rise as soon as the TXEMPTY flag is set.
Problem Fix/Workaround
Use the CS in PIO mode when PDC mode is required and CS has to be maintained between transfers.
40.21.7.4 SPI: SPCK Behavior in Master Mode
SPCK pin can toggle out before the first transfer in Master Mode.
Problem Fix/Workaround
In Master Mode, MSTR bit must be set (in SPI_MR register) before configuring SPI_CSRx registers.
40.21.7.5 SPI: Chip Select and Fixed Mode
In fixed Mode, if a transfer is performed through a PDC on a Chip select different from the Chip select 0, the output
spi_size sampled by the PDC will depend on the field, BITS (Bits per Transfer) of SPI_CSR0 register, whatever the
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
720