SAM7S256_14 Datasheet, PDF (279/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 28-8. Peripheral Deselection
CSAAT = 0
TDRE
NPCS[0..3]
Write SPI_TDR
DLYBCT
A
A
DLYBCS
PCS = A
CSAAT = 1
DLYBCT
A
A
A
DLYBCS
PCS = A
TDRE
NPCS[0..3]
Write SPI_TDR
DLYBCT
A
A
DLYBCS
PCS=A
DLYBCT
A
A
A
DLYBCS
PCS = A
TDRE
DLYBCT
NPCS[0..3]
A
B
DLYBCS
PCS = B
Write SPI_TDR
DLYBCT
A
B
DLYBCS
PCS = B
28.6.3.8 Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external mas-
ter on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the PIO
controller, so that external pull up resistors are needed to guarantee high level.
When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automat-
ically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the
MODFDIS bit in the SPI Mode Register (SPI_MR).
28.6.4 SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the
clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select
Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the
NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers
have no effect when the SPI is programmed in Slave Mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
279