SAM7S256_14 Datasheet, PDF (700/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Problem Fix/Workaround
Do not write 0 in the period register.
40.18.4.3 PWM: Counter Start Value
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1.
Problem Fix/Workaround
None.
40.18.4.4 PWM: Constraints on Duty Cycle Value
Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode
may change the polarity of the signal.
Problem Fix/Workaround
Do not set PWM_CDTYx at 0 in center aligned mode.
Do not set PWM_CDTYx at 0 or 1 in left aligned mode.
40.18.4.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the
PWM_DIS Register just after enabling it (before completion of a Clock Period of the clock selected for the channel),
the PWM line is internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
Problem Fix/Workaround
Do not disable a channel before completion of one period of the selected clock.
40.18.5 Real Time Timer (RTT)
40.18.5.1 RTT: Possible Event Loss when Reading RTT_SR
If an event (RTTINC or ALMS) occurs within the same slow clock cycle during which the RTT_SR is read, the cor-
responding bit might be cleared. This can lead to the loss of this event.
Problem Fix/Workaround:
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
40.18.6 Serial Peripheral Interface (SPI)
40.18.6.1 SPI: Software Reset Must be Written Twice
If a software reset (SWRSTin the SPI Control Register) is performed, the SPI may not work properly (the clock is
enabled before the chip select.
Problem Fix/Workaround
The SPI Control Register field, SWRST needs to be written twice to be set correctly.
40.18.6.2 SPI: Pulse Generation on SPCK
In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows:
– The Baudrate is odd and different from 1
– The Polarity is set to 1
– The Phase is set to 0
Problem Fix/Workaround
None.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
700