SAM7S256_14 Datasheet, PDF (581/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Table 37-23. SSC Timings (Continued)
Symbol Parameter
SSC₇₍₁₎ TK edge to TF/TD (TK input, TF input)
SSC₈
RF/RD setup time before RK edge (RK input)
SSC₉
RF/RD hold time after RK edge (RK input)
SSC₁₀ RK edge to RF (RK input)
SSC₁₁ RF/RD setup time before RK edge (RK output)
SSC₁₂ RF/RD hold time after RK edge (RK output)
SSC₁₃ RK edge to RF (RK output)
Conditions
3.3V domain
1.8V domain
Receiver
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
Min
6 (+3*t_CPMCK)⁽¹⁾⁽²⁾
10 (+3*t_CPMCK)⁽¹⁾⁽²⁾
0
0
t_CPMCK
t_CPMCK
6⁽²⁾
10.5⁽²⁾
26 - t_CPMCK
56.5 - t_CPMCK
t_CPMCK - 10
t_CPMCK - 5.5
0⁽²⁾
0⁽²⁾
Max
29.5 (+3*t_CPMCK)⁽¹⁾⁽²⁾
56 (+3*t_CPMCK)⁽¹⁾⁽²⁾
Units
ns
ns
ns
ns
ns
ns
27⁽²⁾
ns
58⁽²⁾
ns
ns
ns
ns
ns
4⁽²⁾
ns
12⁽²⁾
ns
Notes:
1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7
(Receive Start Selection), two Periods of the MCK must be added to timings.
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabilization. Figure
37-16 illustrates Min and Max accesses for SSC0. The same applies for SSC1, SSC4, and SSC7, SSC10 and SSC13.
3. 3.3V domain: V_VDDIOfrom 3.0V to 3.6V, maximum external capacitor = 40 pF.
4. 1.8V domain: V_VDDIOfrom 1.65V to 1.95V, maximum external capacitor = 20 pF.
5. t_CPMCK: Master Clock period in ns
Figure 37-16. Min and Max access time of output signals
TK (CKI =1)
TK (CKI =0)
TF/TD
SSC_0min
SSC_0max
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
581