SAM7S256_14 Datasheet, PDF (499/775 Pages) ATMEL Corporation – ARM-based Flash MCU

34.6.12 PWM Channel Counter Register
Register Name:
PWM_CCNT[0..X-1]
Access Type:
Read-only
31
30
29
28
27
26
25
24
CNT
23
22
21
20
19
18
17
16
CNT
15
14
13
12
11
10
9
8
CNT
7
6
5
4
3
2
1
0
CNT
• CNT: Channel Counter Register
Internal counter value. This register is reset when:
• the channel is enabled (writing CHIDx in the PWM_ENA register).
• the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
34.6.13 PWM Channel Update Register
Register Name:
PWM_CUPD[0..X-1]
Access Type:
Write-only
31
30
29
28
27
26
25
24
CUPD
23
22
21
20
19
18
17
16
CUPD
15
14
13
12
11
10
9
8
CUPD
7
6
5
4
3
2
1
0
CUPD
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modify-
ing the waveform period or duty-cycle.
Only the first 16 bits (internal channel counter size) are significant.
CPD (PWM_CMRx Register)
0
1
The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the
beginning of the next period.
The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning
of the next period.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
499