SAM7S256_14 Datasheet, PDF (412/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can
generate an external clock on the RK I/O pad.
This allows the SSC to support many Master and Slave Mode data transfers.
32.6.1.1 Clock Divider
Figure 32-4. Divided Clock Block Diagram
Clock Divider
SSC_CMR
MCK
/2
12-bit Counter
Divided Clock
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is
4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is
provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used
and remains inactive.
When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by
2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a
50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd.
Figure 32-5. Divided Clock Generation
Master Clock
Divided Clock
DIV = 1
Divided Clock Frequency = MCK/2
Master Clock
Divided Clock
DIV = 3
Divided Clock Frequency = MCK/6
Table 32-2.
Maximum
MCK / 2
Minimum
MCK / 8190
32.6.1.2 Transmitter Clock Management
The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the
TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register).
Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
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