SAM7S256_14 Datasheet, PDF (618/775 Pages) ATMEL Corporation – ARM-based Flash MCU

– PLL Clock to Main Clock or
– Main Clock to PLL Clock or
– Main Clock to Slow Clock
And
2. Program code is being executed out of flash, or a transition is occurring on PA1, either as an input or
output.
Note: This issue does not occur when transitioning from slow clock to main clock or from slow clock to PLL clock.
Problem Fix/Workaround
When changing CSS in the PMC_MCKR to switch from
– PLL Clock to Slow Clock or
– PLL Clock to Main Clock or
– Main Clock to PLL Clock or
– Main Clock to Slow Clock
Ensure that the processor is executing out of SRAM and ensure no transition occurs on PA1, either as an input or
output, starting from writing to the PMC_MCKR register until MCKRDY = 1.
40.6.7 Pulse Width Modulation Controller (PWM)
40.6.7.1 PWM: Update when PWM_CCNTx = 0 or 1
If the Channel Counter Register value is 0 or 1, the Channel Period Register or Channel Duty Cycle Register is
directly modified when writing the Channel Update Register.
Problem Fix/Workaround
Check the Channel Counter Register before writing the update register.
40.6.7.2 PWM: Update when PWM_CPRDx = 0
When Channel Period Register equals 0, the period update is not operational.
Problem Fix/Workaround
Do not write 0 in the period register.
40.6.7.3 PWM: Counter Start Value
In left aligned mode, the first start value of the counter is 0. For the other periods, the counter starts at 1.
Problem Fix/Workaround
None.
40.6.7.4 PWM: Constraints on Duty Cycle Value
Setting Channel Duty Cycle Register (PWM_CDTYx) at 0 in center aligned mode or at 0 or 1 in left aligned mode
may change the polarity of the signal.
Problem Fix/Workaround
Do not set PWM_CDTYx at 0 in center aligned mode.
Do not set PWM_CDTYx at 0 or 1 in left aligned mode.
40.6.7.5 PWM: Behavior of CHIDx Status Bits in the PWM_SR Register
Erratic behavior of the CHIDx status bit in the PWM_SR Register. When a channel is disabled by writing in the
PWM_DIS Register just after enabling it (before completion of a Clock Period of the clock selected for the channel),
the PWM line is internally disabled but the CHIDx status bit in the PWM_SR stays at 1.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
618