SAM7S256_14 Datasheet, PDF (680/775 Pages) ATMEL Corporation – ARM-based Flash MCU

However, this does not prevent JTAG operations.
Problem Fix/Workaround
The JTAG port remains operational even if the failure on TDI has happened. Therefore the users can develop their
applications in normal conditions, except the overall system power consumption might be higher. It is recom-
mended to handle the devices carefully during PCB soldering and to correctly ground the manufacturing
equipment.
To prevent any failure on the final customer's systems, it is also recommended to tie the TDI pin at GND in the sys-
tem production release and to not pull it up, as it is shown on the SAM7S-EK Evaluation Board schematics.
40.16.3 Master Clock (MCK)
40.16.3.1 MCK: Limited Master Clock Frequency Ranges
If the Flash is operating without wait states, the frequency of the Master Clock MCK must be lower than 3 MHz or
higher than 19 MHz.
If the Flash is operating with one wait state, the frequency of the Master Clock MCK must be lower than 3 MHz or
higher than 19 MHz.
If the Flash is operating with two wait states, the frequency of the Master Clock MCK must be lower than 3 MHz or
higher than 25 MHz.
If the Flash is operating with three wait states, the frequency of the Master Clock MCK must be lower than 3 MHz
or higher than 38 MHz.
If these constraints are not respected, the correct operation of the system cannot be guaranteed and either data or
prefetch abort might occur.
The maximum operating frequencies (at 30 MHz @ 0 Wait States and 55 MHz @ 1 Wait State) as stated in
Table 37-24, “Embedded Flash Wait States,” on page 582, are still applicable.
Note: It is not necessary to use 2 o 3 wait states because the Flash can operate at maximum frequency with only 1 wait state.
Problem Fix/Workaround
The user must ensure that the device is running at the authorized frequency by programming the PLL properly to
not run within the forbidden frequency range.
40.16.4 Non Volatile Memory Bits (NVM Bits)
40.16.4.1 NVM Bits: Write/Erase Cycles Number
The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes Lock Bits (LOCKx),
General Purpose NVM bits (GPNVMx) and the Security Bit.
This maximum number of write/erase cycles is not applicable to 64 KB Flash memory, it remains at10K for the
Flash memory.
Problem Fix/Workaround
None.
40.16.5 Parallel Input/Output Controller (PIO)
40.16.5.1 PIO: Leakage on PA17 - PA20
When PA17, PA18, PA19 or PA20 (the I/O lines multiplexed with the analog inputs) are set as digital inputs with
pull-up disabled, the leakage can be 9 µA in worst case and 90 nA in typical case per I/O when the I/O is set exter-
nally at low level.
Problem Fix/Workaround
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
680