SAM7S256_14 Datasheet, PDF (395/775 Pages) ATMEL Corporation – ARM-based Flash MCU

31.7.4 USART Interrupt Disable Register
Name:
US_IDR
Access Type:
Write-only
31
30
29
28
27
–
–
–
–
–
23
22
21
20
19
–
–
–
–
CTSIC
15
14
13
12
11
–
–
NACK
RXBUFF
TXBUFE
7
PARE
6
FRAME
5
OVRE
4
ENDTX
3
ENDRX
Note: 1. DCDIC, DSRIC and RIIC do not pertain to the SAM7S32/16.
• RXRDY: RXRDY Interrupt Disable
• TXRDY: TXRDY Interrupt Disable
• RXBRK: Receiver Break Interrupt Disable
• ENDRX: End of Receive Transfer Interrupt Disable
• ENDTX: End of Transmit Interrupt Disable
• OVRE: Overrun Error Interrupt Disable
• FRAME: Framing Error Interrupt Disable
• PARE: Parity Error Interrupt Disable
• TIMEOUT: Time-out Interrupt Disable
• TXEMPTY: TXEMPTY Interrupt Disable
• ITERATION: Iteration Interrupt Disable
• TXBUFE: Buffer Empty Interrupt Disable
• RXBUFF: Buffer Full Interrupt Disable
• NACK: Non Acknowledge Interrupt Disable
• RIIC: Ring Indicator Input Change Disable
• DSRIC: Data Set Ready Input Change Disable
• DCDIC: Data Carrier Detect Input Change Interrupt Disable
• CTSIC: Clear to Send Input Change Interrupt Disable
26
–
18
DCDIC ⁽¹⁾
10
ITERATION
2
RXBRK
25
–
17
DSRIC ⁽¹⁾
9
TXEMPTY
1
TXRDY
24
–
16
RIIC ⁽¹⁾
8
TIMEOUT
0
RXRDY
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
395