SAM7S256_14 Datasheet, PDF (489/775 Pages) ATMEL Corporation – ARM-based Flash MCU

34.5.3.4 Interrupts
Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the correspond-
ing channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs.
A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is dis-
abled by setting the corresponding bit in the PWM_IDR register.
34.6 Pulse Width Modulation Controller (PWM) User Interface
Table 34-2. Register Mapping
Offset⁽¹⁾
Register
Name
0x00
PWM Mode Register
PWM_MR
0x04
PWM Enable Register
PWM_ENA
0x08
PWM Disable Register
PWM_DIS
0x0C
PWM Status Register
PWM_SR
0x10
PWM Interrupt Enable Register
PWM_IER
0x14
PWM Interrupt Disable Register
PWM_IDR
0x18
PWM Interrupt Mask Register
PWM_IMR
0x1C
PWM Interrupt Status Register
PWM_ISR
0x4C - 0xFC
Reserved
–
0x100 - 0x1FC
Reserved
0x200 + ch_num * 0x20 + 0x00 PWM Channel Mode Register
PWM_CMR
0x200 + ch_num * 0x20 + 0x04 PWM Channel Duty Cycle Register
PWM_CDTY
0x200 + ch_num * 0x20 + 0x08 PWM Channel Period Register
PWM_CPRD
0x200 + ch_num * 0x20 + 0x0C PWM Channel Counter Register
PWM_CCNT
0x200 + ch_num * 0x20 + 0x10
PWM Channel Update Register
PWM_CUPD
Note: 1. Some registers are indexed with “ch_num” index ranging from 0 to X-1.
Access
Read/Write
Write-only
Write-only
Read-only
Write-only
Write-only
Read-only
Read-only
–
Read/Write
Read/Write
Read/Write
Read-only
Write-only
Reset
0
-
-
0
-
-
0
0
–
0x0
0x0
0x0
0x0
-
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
489