SAM7S256_14 Datasheet, PDF (319/775 Pages) ATMEL Corporation – ARM-based Flash MCU

30. Two Wire Interface (TWI) SAM7S161/16
NOTE: This definition of the TWI does not pertain to SAM7S512/256/128/65/32/321. For
SAM7S512/256/128/65/32/321, see Section 29.
30.1
Overview
The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock
line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can
be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time
Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is pro-
grammable as a master or a slave with sequential or single-byte access. Multiple master capability is supported.
Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is
lost.
A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock
frequencies.
Below, Table 30-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I2C compat-
ible device.
Table 30-1. Atmel TWI compatibility with i2C Standard
I2C Standard
Atmel TWI
Standard Mode Speed (100 KHz)
Supported
Fast Mode Speed (400 KHz)
Supported
7 or 10 bits Slave Addressing
START BYTE⁽¹⁾
Supported
Not Supported
Repeated Start (Sr) Condition
Supported
ACK and NACK Management
Supported
Slope control and input filtering (Fast mode)
Not Supported
Clock stretching
Supported
Note: 1. START + b000000001 + Ack + Sr
30.2 List of Abbreviations
Table 30-2. Abbreviations
Abbreviation
TWI
A
NA
P
S
Sr
SADR
ADR
R
W
Description
Two-wire Interface
Acknowledge
Non Acknowledge
Stop
Start
Repeated Start
Slave Address
Any address except SADR
Read
Write
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
319