SAM7S256_14 Datasheet, PDF (44/775 Pages) ATMEL Corporation – ARM-based Flash MCU

• two interrupt disable bits (one for each type of interrupt)
• one bit to indicate ARM or Thumb execution
• five bits to encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task
immediately preceding the exception.
11.2.4.3 Exception Types
The ARM7TDMI supports five types of exception and a privileged processing mode for each type. The types of
exceptions are:
• fast interrupt (FIQ)
• normal interrupt (IRQ)
• memory aborts (used to implement memory protection or virtual memory)
• attempted execution of an undefined instruction
• software interrupts (SWIs)
Exceptions are generated by internal and external sources.
More than one exception can occur in the same time.
When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save
state.
To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be
done in two ways:
• by using a data-processing instruction with the S-bit set, and the PC as the destination
• by using the Load Multiple with Restore CPSR instruction (LDM)
11.2.5 ARM Instruction Set Overview
The ARM instruction set is divided into:
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]).
Table 11-2 gives the ARM instruction mnemonic list.
Table 11-2.
Mnemonic
MOV
ADD
SUB
RSB
CMP
TST
ARM Instruction Mnemonic List
Operation
Move
Add
Subtract
Reverse Subtract
Compare
Test
Mnemonic
CDP
MVN
ADC
SBC
RSC
CMN
Operation
Coprocessor Data Processing
Move Not
Add with Carry
Subtract with Carry
Reverse Subtract with Carry
Compare Negated
SAM7S Series [DATASHEET] 44
6175M–ATARM–26-Oct-12