SAM7S256_14 Datasheet, PDF (760/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Version
6175F
Comments
“Features” on page 1 (global) QFN packages changed to 64- and 48-pad QFN
Manchester Encoder/Decoder removed from USART.
“Features” on page 1, Table 1-1, “Configuration Summary,” on page 3, Section 4. ”Package and
Pinout”Section 39. ”SAM7S Ordering Information”and global, AT91SAM7S512 added to product family.
Section 4.1 ”64-lead LQFP and 64-pad QFN Package Outlines” and Section 4.3 ”48-lead LQFP and 48-
pad QFN Package Outlines”added (replace Mechanical Overview).
Figure 8-1 on page 20 Peripheral and System Controller Memory Mapping has been condensed.
Section 20. ”Embedded Flash Controller (EFC)” EFC0 and EFC1 on AT91SAM7S512 explained.
Section 10.1 ”User Interface”User Peripherals are mapped between 0xF000 0000 and 0xFFFF EFFF.
Table 10-1 and Table 10-2 SYSIRQ changed to SYSC in “Peripheral Identifiers”
ADC Block diagram Figure 35-1 on page 479 - dedicated and I/O analog inputs differentiated
”ADC Timings” page 485 WARNING”...See the section ADC Characteristics....” typo fixed.
Section 21. ”Fast Flash Programming Interface (FFPI)”, AT91SAM7S512 instructions added to Section
21.2.5.6, and Section 21.2.5.7 on page 155, Section 21.3.4.6 and Section 21.3.4.7 on page 162.
Table 21-1 on page 147 PMD and PGMNVALID bus size for AT91SAM7S32 is [7:0].
AIC, Section 24.7.3.1 ”Priority Controller” SRCTYPTE field is in AIC_SMR register, not AIC_SVR
“Advanced Interrupt Controller (AIC) User Interface” , Table 24-2 on page 198 note 2 ref to PID bit fields
AT91SAM7 Boot Program Section 22.5 ”SAM-BA Boot” SAM-BA boot principle changed Section 22.2
”Flow Diagram”replaced Figure 22-1 and Figure 22-2 on page 165
DBGU: ”ARCH: Architecture Identifier” page 259: updated
Functional Block Diagram in Figure 27-1 on page 238 and Section 27.5.12 ”Debug Unit Force NTRST
Register”ice_nreset signal replaced with pad name, Power-on Reset (power_on_reset.)
“Peripheral DMA Controller (PDC)” User interface description updated page 173. Correct typo to
“ENDTX” bit field name in Section 23.3.3 ”Transfer Counters”
PIO, Section 15.4.4 ”Output Control” typo corrected
Section 15.4.1 ”Pull-up Resistor Control”, ref to resistor value removed.
Figure 15-3 ”I/O Line Control Logic” page 82, 0 and 1 inverted in the MUX controlled by PIO_MDSR.
”PMC Master Clock Register” on page 231 Corrected name of bitfield “PRES”
Note defining PIDx added to “PMC Peripheral Clock Enable Register” , ”PMC Peripheral Clock Disable
Register” page 226 and
Table 26-2 on page 222: footnotes reassigned.
PWM, updated waveform generation Section 33.5.3.3 ”Changing the Duty Cycle or the Period” page 430.
RSTC; added info on startup counter on crystal oscillator Section 13.3.1 ”Reset Controller Overview”
RTT, added note to ”Functional Description” page 73
SPI, Figure 28-9 ”Slave Mode Functional Block Diagram” page 272, FLOAD removed
Section 28.6.3 ”Master Mode Operations” change to SPI_RDR information
Section 28.7.1 ”SPI Control Register” added information to bit description ”SWRST: SPI Software Reset”
page 14.
Section 28.7.9 ”SPI Chip Select Register” corrected equation in ”DLYBCT: Delay Between Consecutive
Transfers” page 25.
Section 28.6.3.8 ”Mode Fault Detection” updated
SSC, Section 31.6.6.1 ”Compare Functions” updated
Change
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IP update
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
760