SAM7S256_14 Datasheet, PDF (653/775 Pages) ATMEL Corporation – ARM-based Flash MCU

40.11.11 Two-wire Interface (TWI)
40.11.11.1 TWI: Clock Divider
The value of CLDIV x 2^CKDIV must be less than or equal to 8191, the value of CHDIV x 2^CKDIV must be less than or
equal to 8191⋅
Problem Fix/Workaround
None.
40.11.11.2 TWI: Software Reset
When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new trans-
fer in READ or WRITE mode.
Problem Fix/Workaround
None.
40.11.11.3 TWI: Disabling Does not Operate Correctly
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1.
Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled
before disabling the TWI.
40.11.11.4 TWI: NACK Status Bit Lost
During a master frame, if TWI_SR is read between the Non Acknowledge condition detection and the TXCOMP bit
rising in the TWI_SR, the NACK bit is not set.
Problem Fix/Workaround
The user must wait for the TXCOMP status bit by interrupt and must not read the TWI_SR as long as transmission
is not completed.
TXCOMP and NACK fields are set simultaneously and the NACK field is reset after the read of the TWI_SR.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
653