SAM7S256_14 Datasheet, PDF (596/775 Pages) ATMEL Corporation – ARM-based Flash MCU

40.2 Errata Summary by Product and Revision or Manufacturing Number
Table 40-1.
Errata Summary Table
SAM7Sx Product
Revision or Manufacturing Number
Part
Errata
Chip ID
Wrong Chip ID Value
XX
ADC
DRDY Bit Cleared
XXXXX
XXX
XX X
ADC
DRDY not Cleared on Disable
XXXXX
XXX
XX X
ADC
DRDY Possibly Skipped due to CDR Read
XXXXX
XXX
XX X
ADC
Possible Skip on DRDY when Disabling a Channel
XXXXX
XXX
XX X
ADC
GOVRE Bit is not Updated
XXXXX
XXX
XX X
ADC
GOVRE Bit is not Set when Reading CDR
XXXXX
XXX
XX X
ADC
GOVRE Bit is not Set when Disabling a Channel
XXXXX
XXX
XX X
ADC
OVRE Flag Behavior
XXXXX
XXX
XX X
ADC
EOC Set although Channel Disabled
XXXXX
XXX
XX X
ADC
Spurious Clear of EOC Flag
XXXXX
XXX
XX X
ADC
Sleep Mode
XXXXX
XXX
XX X
EFC
Embedded Flash Access Time 1
Embedded Flash Access Time 2
X
X
XX
JTAG
Recommendation for TDI Pin
X
MCK
Limited Master Clock Frequency Ranges
X
X
NVM Bits Write/Erase Cycles Number
XXX
XXX
X
PIO
Leakage on PA17 - PA20
XXXX
XX
X
PIO
Electrical Characteristics on NRST and PA0-PA16 and
PA21-31
XXXXXXXXXXX X X
PIO
Drive Low NRST, PA0-PA16 and PA21-PA31
XXXXXXXXXXX X X
PMC
Slow Clock Selected in PMC and a Transition Occurs on
PA1
XX
PMC
Programming CSS in PMC_MCKR Register
XX
PWM
Update when PWM_CCNTx = 0 or 1
XXXXXXXXXXX X X X
PWM
Update when PWM_CPRDx = 0
XXXXXXXXXXX X X X
PWM
Counter Start Value
XXXXXXXXXXX X X X
PWM
Constraints on Duty Cycle Value
XXXXX
XXX
XX X
PWM
Behavior of CHIDx Status Bits in the PWM_SR Register X X X X X
XXX
XX X
RTT
Possible Event Loss when Reading RTT_SR
XXXXXXXXX X X X
RTT
RTT_VR May be Corrupted
XX
SPI
Software Reset Must be Written Twice
XX
X
X
X
SPI
Pulse Generation on SPCK
XXX
XX
SPI
Bad Behavior when CSAAT = 1 and SCBR = 1
XXXXX
XXX
XX
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
596