SED1374 Datasheet, PDF (95/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 87
13.6 Clock Requirements
The following table shows what clock is required for which function in the SED1374.
Table 13-5: SED1374 Internal Clock Requirements
Function
Register Read/Write
Memory Read/Write
Software Power Save
Hardware Power Save
BCLK
CLKI
Is required during register accesses. BCLK
can be shut down between accesses: allow
eight BCLK pulses plus 12 MCLK pulses
(8T_BCLK + 12T_MCLK) after the last access
before shutting BCLK off. Allow one BCLK
pulse after starting up BCLK before the next
access
Not Required
Is required during memory accesses. BCLK
can be shut down between accesses: allow
eight BCLK pulses plus 12 MCLK pulses
(8T_BCLK + 12T_MCLK) after the last access
before shutting BCLK off. Allow one BCLK
pulse after starting up BCLK before the next
access
Required
Required
Can be stopped after 128 frames from
entering Software Power Save, i.e. after
REG[03h] bits 1-0 = 11
Not Required
Can be stopped after 128 frames from
entering Hardware Power Save
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02