SED1374 Datasheet, PDF (347/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
4 MPC821 to SED1374 Interface
Page 15
4.1 Hardware Description
The interface between the SED1374 and the MPC821 requires minimal glue logic. One
inverter is required to change the polarity of the WAIT# signal (an active low signal) to
insert wait states in the bus cycle. The MPC821 Transfer Acknowledge signal (TA) is an
active low signal which ends the current bus cycle. The inverter is enabled using CS# so
that TA is not driven by the SED1374 during non-SED1374 bus cycles. A single resistor is
used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle.
BS# (bus start) is not used in this implementation and should be tied low (connected to
GND).
The following diagram shows a typical implementation of the MPC821 to SED1374
interface.
MPC821
A[16:31]
D[0:15]
CS4
TA
WE0
WE1
OE
SYSCLK
RESET
Vcc
470
SED1374
AB15-AB0
DB[15:D0]
CS#
WAIT#
WE1#
WE0#
RD/WR#
RD#
BUSCLK
RESET#
Figure 4-1: Typical Implementation of MPC821 to SED1374 Interface
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-010-02