SED1374 Datasheet, PDF (44/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 36
7.3.2 Power Down/Up Timing
Epson Research and Development
Vancouver Design Center
LCDPWR Override
(REG[03h] bit 3)
HW Power Save
or
Software Power Save
REG[03h] bits [1:0] ¹¹
00
11
00
t1
t2
FP Signals Active
Inactive
Active
Inactive
t3
t4
t5
t6
LCDPWR
(polarity set by CNF4)
Active
Inactive
Active
Inactive
11
Active
t7
Active
Figure 7-9: Power Down/Up Timing
Table 7-8: Power Down/Up Timing
Symbol
Parameter
Min
Typ
Max Units
t1
HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
inactive - LCDPWR Override = 1
1
Frame
t2
HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
active - LCDPWR Override = 1
1
Frame
t3
HW Power Save active to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
inactive - LCDPWR Override = 0
1
Frame
t4
LCDPWR low to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY inactive
- LCDPWR Override = 0
127
Frame
t5
HW Power Save inactive to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY,
LCDPWR active - LCDPWR Override = 0
0
Frame
t6 LCDPWR Override active (1) to LCDPWR inactive
1
Frame
t7 LCDPWR Override inactive (1) to LCDPWR active
1
Frame
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29