SED1374 Datasheet, PDF (416/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 12
Epson Research and Development
Vancouver Design Center
4.2 SED1374 Hardware Configuration
The SED1374 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the SED1374 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show only those configuration settings important to the 8-bit processor
interface. The endian must be selected based on the 8-bit processor used.
Signal
CNF0
CNF1
CNF2
CNF3
CNF4
Table 4-1: Configuration Settings
Low
High
See “Host Bus Selection” table below See “Host Bus Selection” table below
Little Endian
Active low LCDPWR signal
Big Endian
Active high LCDPWR signal
= configuration for 8-bit processor host bus interface
CNF2
1
CNF1
1
Table 4-2: Host Bus Selection
CNF0
1
BS#
Host Bus Interface
1
Generic #2, 16-bit
= required configuration for this application.
4.3 Register/Memory Mapping
The SED1374 needs a 64K byte block of memory to accommodate its 40K byte display
buffer and its 32 byte register set. The starting memory address is located at 0000h of the
64K byte memory block while the internal registers are located in the upper 32 bytes of this
memory block. (i.e. REG[0]= FFE0h).
An external decoder can be used to decode the address lines and generate a chip select for
the SED1374 whenever the selected 64K byte memory block is accessed. If the processor
supports a general chip select module, its internal registers can be programmed to generate
a chip select for the SED1374 whenever the SED1374 memory block is accessed.
SED1374
X26A-G-013-01
Interfacing to an 8-bit Processor
Issue Date: 99/05/04