SED1374 Datasheet, PDF (45/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
7.3.3 Single Monochrome 4-Bit Panel Timing
Page 37
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:4]
VDP
VNDP
LINE1 LINE2 LINE3 LINE4
LINE239 LINE240
LINE1 LINE2
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
1-1 1-5
1-2 1-6
1-3 1-7
1-4 1-8
HDP
HNDP
1-317
1-318
1-319
1-320
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
Figure 7-10: Single Monochrome 4-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02