SED1374 Datasheet, PDF (351/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 19
4.4 MPC821 Chip Select Configuration
The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh, so the
SED1374 is addressed starting at 40 0000h. The SED1374 uses a 64K byte segment of
memory starting at this address, with the first 40K bytes used for the display buffer and the
upper 32 bytes of this memory block used for the SED1374 internal registers.
Chip select 4 is used to control the SED1374. The following options are selected in the base
address register (BR4):
• BA (0:16) = 0000 0000 0100 0000 0 – set starting address of SED1374 to 40 0000h
• AT (0:2) = 0 – ignore address type bits
• PS (0:1) = 1:0 – memory port size is 16 bits
• PARE = 0 – disable parity checking
• WP = 0 – disable write protect
• MS (0:1) = 0:0 – select General Purpose Chip Select module to control this chip select
• V = 1 – set valid bit to enable chip select
The following options were selected in the option register (OR4):
• AM (0:16) = 1111 1111 1100 0000 0 – mask all but upper 10 address bits; SED1374
consumes 4M byte of address space
• ATM (0:2) = 0 – ignore address type bits
• CSNT = 0 – normal CS/WE negation
• ACS (0:1) = 1:1 – delay CS assertion by ½ clock cycle from address lines
• BI = 1 – assert Burst Inhibit
• SCY (0:3) = 0 – wait state selection; this field is ignored since external transfer
acknowledge is used; see SETA below
• SETA = 1 – the SED1374 generates an external transfer acknowledge using the WAIT#
line
• TRLX = 0 – normal timing
• EHTR = 0 – normal timing
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-010-02